1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, an approach to logic design for a semiconductor integrated circuit.
2. Description of the Related Art
The manufacture of semiconductor devices is advanced basically in compliance with a flowchart in FIG. 1 showing production processes. In other words, irrespective of difference between automatic design and manual design, the semiconductor devices can be designed via functional design process, logic design process, layout design process, device design process, circuit design process, and testing design process. In the functional design process, function specifications of the semiconductor integrated circuit are determined according to system specifications and then detailed operations of the semiconductor integrated circuit are designed. The architecture of the semiconductor integrated circuit such as bit widths/number of registers in logic blocks, number/usage of control lines and bus lines, type/usage of clock, etc. are determined via the functional design process. In the logic design process, the semiconductor integrated circuit is embodied up to a circuit level in units of logic gates such as NAND circuits, inverter circuits, etc. based on functional design data. In the logic design process, design will be made with interconnections between the logic gates, i.e., a logic circuit structure as its chief purpose. Basic logic gates used in the logic design process are selected from a menu in a logic cell library which has prepared in advance via the device design and the circuit design. Respective cells such as complex gate, flip-flop, tri-state driver in addition to simple basic logic gates are included on the scale of several to ten and over logic gates in the logic cell library.
In the logic design process, respective delay values of the logic gates which can be predicted based on their electrical performance are assigned to respective logic gates to run a delay simulation, so that elimination of logic error can be assured. However, since media delay, etc. which cannot be fixed until the layout design has been finished cannot sufficiently be evaluated at this stage, in many cases detailed simulation is done once again after the layout design to check firmly logic error. In the device design process, profile, electrical performance, etc. of transistors to be used can be designed according to manufacturing conditions of the semiconductor integrated circuit. Usually, proper transistors are selected from a transistor menu which corresponds to capability of the manufacturing line. But new transistors are designed if they are insufficient in performance. The circuit design process is made up of two procedures of basic circuit or circuit cell design and whole circuit design. The layout design process is most important throughout design processes of the semiconductor integrated circuit. The layout design process is an operation to design mask patterns for use in the semiconductor integrated circuits. With the use of the connectivity list obtained by the logic design process and the logic cell library which has been prepared by the circuit design process, placement and routing of the logic gates are accomplished. As for data collected after the layout design process has been terminated, electrical performance of the logic gates is verified by logic simulator, circuit simulator, or the like. The process then turns to the logic design process if any deficiency has been detected. The data are then transferred as the mask patterns to production process after the layout design process has been completed.
In the testing design process, testing patterns are designed to check whether or not the manufactured semiconductor integrated circuit has satisfied expected performance and function.
In turn, the process goes to the production testing process after the design processes have been completed. First, the chip manufacturing process is carried out in which chips are manufactured in accordance with manufacturing conditions. Then, the process advances to testing evaluation process in which the chips are evaluated according to the testing design process, whereby a product can be finished.
Logic synthesis process which is automated technology in the logic design process has been recognized as a design phase prior to layout design process. According to the logic synthesis circuits at detailed gate level can be constituted of descriptions at an upper level, e.g., descriptions at a register transfer level. In recent years, influence of routings on signal propagation delay, area of the semiconductor integrated circuit, and power consumption is being increased with the progress of miniaturization and high integration density of the semiconductor integrated circuit.
In order to avoid such influence, such an approach has been proposed that the logic synthesis process is tried once again with regard to the layout design (Link-to-Layout Logic Synthesis Approach, SYNOPSYS Corp.). However, the layout design process must be tried entirely once more since the logic synthesis process has to be reconsidered from the beginning in this approach. Therefore, such approach would result in certainly another placement and routing which are different from those obtained by the first logic synthesis.
Consequently, sometimes the logic synthesis process and the layout design process must be made over further more. In this manner, there can be no guarantee to converge such processes, so that a process time required for the logic synthesis process and the layout design process is increased several times. Thus, such approach would be inadvisable in respect of the process time.
Furthermore, another approach has also been proposed in which the logic synthesis process and the layout design process are carried out completely simultaneously (M. Pedram et al., "Layout Driven Logic Restructuring/Decomposition", ICCAD 91). However, since basic logic gates which are intermediate representations in the logic synthesis are placed as they are in this approach, the number of devices to be subjected to the layout design process is increased rather than the number of devices in usual design flow. Therefore, it takes a lot of process time to carry out the layout design process itself. Also it takes a lot of process time to carry out the logic synthesis process per se since the logic synthesis is advanced while performing the layout design of all the logic circuits. In addition, the synthesis results are the results of layout design in this approach, but there can be no guarantee of quality of the results of layout design. There is a possibility that the layout design process must be done over again to arrange the logic circuits in a small area.
As still another approach, in order to reduce influence of the routings on the signal propagation delay particularly, such technique has existed that the logic gates located in a part of the logic circuit are replaced, otherwise buffers are inserted into concerned parts after the layout design process has been effected once more (Patent Application No. Hei 5-227077, Laid-open No. Hei 7-86410). However, a combination of logic circuits to achieve function is not modified in this technique. Hence, appropriate improvements cannot be introduced in this technique such that in the area to which a plenty of routings are to be assigned, a combination of logic gates with fewer routings is employed to improve a routing complexity degree at a slight sacrifice of signal propagation delay, or conversely, in the area to which fewer routings are to be assigned, another combination of logic gates is employed to reduce signal propagation delay even if the number of routings are increased. In addition, the combination of logic gates cannot be modified to take account of minimization of a switching factor of the signal. In this manner, it is difficult only by replacing a part of the logic gates simply that the routing complexity degree may be relaxed or the semiconductor integrated circuit with low power consumption may be accomplished.
As an automatic logic synthesis approach in the prior art, there has been known a processing approach which is called "technology mapping". According to this automatic logic synthesis approach, abstract logic functions which do not have size and physical information and are composed of AND operator, OR operator, NOT operator are embodied by logic gates which have physical substance.
As an ordinary approach of the technology mapping such an approach has been proposed that logic functions composed of AND operators, etc. can be represented intermediately by two basic logic gates, i.e., NAND2s (two-input NAND circuits) and IVs (inverters) after the logic design process has been effected but before the layout design process is effected and thereafter the logic functions are replaced with the logic gates having physical substance by making use of DAG (Directed Acyclic Graph) mapping (Keutzer DAC' 87 DAGON: Technology Binding and Logic Optimization by DAG Mapping). However, in this approach, there has been a problem that the results of layout design process cannot be taken into account.
As design evaluation indices for the semiconductor integrated circuit, area (integration density), signal propagation delay time, power consumption, for example, may be considered. A smaller area of the semiconductor integrated circuit (i.e., higher integration density) can make the production cost lower. In addition, a shorter signal propagation delay time can make operation speed of the semiconductor integrated circuit higher. As a result, design of high performance semiconductor integrated circuit can be accomplished.
Furthermore, since smaller power consumption enables a longer time duration of the circuit if the circuit is incorporated into a battery-powered system, for example, higher facility can be attained. Still further, since the cost of design and package for heat radiation can be reduced, the semiconductor integrated circuit can be manufactured at low cost. It has been known that, at the stage that the logic design process has been terminated, it is difficult to estimate influence of routings on these evaluation indices precisely. Therefore, this fact has been a major factor to increase a design time of the semiconductor integrated circuit.
As for the area, it has been known empirically in layout design that a higher routing complexity degree makes routing itself more difficult and makes a rate of a routing area to a total area higher and in its turn brings about increase of the area. As for the signal propagation delay, there has existed influence of wiring capacitance on the signal propagation delay. As for the power consumption, increase of power consumption due to charge/discharge of wiring capacitance has been known.
With the above discussion, it would be important for design of the semiconductor integrated circuit with good evaluation indices to carry out logic resynthesis process with regard to the results of layout design process, more particularly, while estimating precisely routing complexity degree, wiring capacitance values, and in its turn final area (integration degree), signal propagation delay time, power consumption, etc. in the course of logic synthesis process.